Many solid-state and quantum technologies require multiple control and signal lines to allow transitioning from room temperature to a cryogenic environment. As the number of individual devices increases, there is a problem of depleting resources, such as cooling power and physical space.

This is especially a problem if non-uniformity of individual devices limits the extent to which common control voltages can be used. An example of such a technology is a semiconductor spin qubit based on a gate-defined quantum dot (QD) device. It may require numerous gates to define the necessary potential landscape for one QD, and the voltage on each gate requires precise tuning to operate the QD. This is an issue for single devices that only increases as the technology gets scaled up.

A novel solution is to employ charge-locking circuitry to provide individual tunability. Each charge-locking unit, formed of a multiplexer and an array of charge-locking units, can be set to a different voltage. However, this set up requires power to be dissipated periodically to discharge the charge-locking units. The power dissipation causes a problem as it requires a large amount of cooling power as the number of units grows, and adds to the total recharge time.

Researchers at Oxford have devised a novel charge-locking array circuit design to address the problems above.

The circuit design features two sets of multiplexed interconnects that are configured in a circuit consisting of a row of recharging capacitors and an array of holding capacitors. Through a specific sequence to operate the multiplexer, each recharging capacitor can be set to hold different static voltage, which can in turn be used to compensate the voltage drift in a row of holding capacitors. The recharging of holding capacitors takes place row-wise by charge redistribution between recharging capacitors and holding capacitors when electrical connections are established.

There are huge advantages of this novel design:

• a parallel recharged (refreshed) 1D or 2D array, the energy dissipation rate is about 400 times lower than conventional arrays
• a more than 5000 times reduction in power dissipation has been modelled for 214×214 charge-locking units (i.e. ~2.6×108 charge-locking units) and a transistor gate of 10nm×14nm (gate capacitance ~1.4×10−3fF)